1. Field of the Invention
This invention relates to computer systems and, more particularly, to an arrangement for varying semiconductor chip characteristics based on attributes determined by monitoring the chip in operation.
2. History of the Prior Art
A modern computer is typically constructed from a plurality of modular semiconductor chip components connected together in circuit by means such as conductive traces arranged on a circuit board. For example, a computer may include a modular microprocessor chip, a plurality of memory chips, various input/output devices each including chips providing electronic circuitry for controlling the device, and other circuitry joined together to provide a system for manipulating data in response to instructions.
In order to assure that the circuit elements of each of the chips function together to provide a system which correctly manipulates data, each of the different chips includes interface circuitry adapted to correctly handle and interpret signals received from and sent to circuit elements on the other chips of the system. For example, memory circuits are designed to respond to signals provided at particular voltage and current levels which appear at particular input terminals at particular times with respect to other signals. In order to cause the memory circuits to respond correctly, the signals must fall within the expected ranges and must appear at the correct times with respect to other signals.
Chip manufacturers provide specifications which define the signals with which circuits on their chips will function correctly. Among these specifications are characteristics called “output valid time” and “output hold time.” As is illustrated in FIG. 1, output valid time measures the period after a clock signal before valid data is guaranteed at a terminal; data received before this period has ended may not be properly processed by the chip. Output hold time measures a period after a next clock signal during which data is guaranteed to remain valid. In order to function properly with signals received from circuitry on another chip, the output circuitry of the other chip must provide signals meeting these and other specifications.
A chip designer can assure that a chip will meet the design specifications for an interface with another chip only by providing output (and input) characteristics which meet the specifications of the other chip. Thus, a chip designer must assure that the output data it produces for another chip comply with, among other things, the input setup and input hold times specified for that other chip. The designer must assure that the delays provided in the data output paths comply with the specifications for the other chip.
If a chip is to interface with a number of different chips serving the same purpose (e.g., memory chips from different manufacturers), then the chip must meet the specifications of all of the different chips. Often these specifications vary sufficiently that reaching this result is quite difficult.
For example, the propagation characteristics of signals provided by a particular chip depend upon a number of factors including the particular process used in the manufacture of the chip, the voltage of operation, and the temperature of operation. As these factors vary during operation, so do the propagation characteristics of the chip and its ability to meet the specifications required by the various interfaces with other chips.
In order to assure that their chips are able to meet the specifications of a variety of other chips, prior art designers have provided a number of different solutions. One technique which has been utilized selects from among a plurality of output paths having different delay characteristics measured in hardware during operation.
The ability to meet interface specifications is made even more difficult as computer systems become more advanced. For example, each step in the constant increase in system clock frequencies utilized by computers makes it more difficult to meet both the output valid time and the output hold time specifications of an interface. Although it becomes easier to assure that valid data reaches another chip by the specified time as silicon speed rises, it becomes more difficult to guarantee that the data will remain for a specified hold time. It has become necessary in many cases to provide latching circuitry to meet specified hold times. However, when a chip is to operate with other chips having different characteristics, the need to provide circuitry to meet the specifications of each of the different chips becomes overwhelmingly complicated.
To meet this problem, an advanced arrangement, described in U.S. Pat. No. 5,180,937, entitled Delay Compensator and Monitor Circuit Having Timing generator and Sequencer, Laird, et al., issued Jan. 19, 1993 includes a plurality of delay lines that are monitored during operation of circuitry on a chip to provide an output indicative of the operating speed of the chip. More particularly, the different delay lines provide output signals which are longer than, near to, or shorter than a measurement period. These outputs are utilized by a timing synchronizer circuit (a state machine) to determine whether the circuitry on the chip is running at a fast or slow rate. The result provided by the timing synchronizer circuit (a state machine) to determine whether the circuitry on the chip is running at a fast or slow rate. The result provided by the timing synchronizer circuitry is then used to the delay which is selected for an output circuit in order to match the specifications for output valid time and output hold time required by interfaces to other chips during the operation of the chip being controlled. In one embodiment, the timing synchronizer selects a delay line to be inserted in a path controlling the timing for a latch in the output path based on the results obtained through the controlled measurements of the output of the monitoring delay lines.
The circuitry described in this patent helps significantly to increase the ability of semiconductor chips to meet specifications for interfaces with other chips. However, it is quite difficult to provide the ability for such circuitry to manipulate circuitry characteristics over more than limited ranges of operating conditions without the cost becoming too great and the circuitry too large.
Moreover, an even more difficult problem has been raised by a recent advance in the computer art. A new microprocessor has been developed which combines a simple but fast host processor (called a “morph host”) and software (called “code morphing software”) to execute application programs designed for a processor having a different instruction set at a rate equivalent to the processor for which the programs were designed (the target processor). The morph host processor executes the code morphing software to translate the target application programs into morph host processor instructions which accomplish the purpose of the original target software. As the target instructions are translated, they are stored in a translation buffer where they may be accessed without further translation. The resulting translations are then executed and perform the same functions that they would on a processor that implemented the target architecture in hardware. Although the initial translation and execution of a program may be slow, once translated, many of the steps normally required to execute a program in hardware are eliminated. The new processor is described in detail in U.S. Pat. No. 6,031,992, entitled Combining Hardware And Software To Provide An Improved Microprocessor, Cmelik et al, issued Feb. 29, 2000, and assigned to the assignee of the present application.
Because of its design, the new microprocessor utilizes many fewer circuit elements than do competitive processors. Consequently, it uses much less power than prior art processors to accomplish similar operations. An enhancement to this microprocessor further reduces its power dissipation and allows the microprocessor to run for significantly-extended periods using limited power sources such as batteries. This enhancement constantly monitors system operation and adjusts both the system voltage and operating frequency based on the requirements of the system as it operates. This enhancement is described in U.S. patent application Ser. No. 09/484,516, entitled Adaptive Power Control, S. Halepete et al, filed Jan. 18, 2000, and assigned to the assignee of the present invention. Because this power-conserving enhancement constantly varies frequency and voltage, the various propagation characteristics of the system which control the ability of the chip to meet interface specifications may also vary constantly.
It is therefore desirable to provide improved arrangements for controlling the characteristics of semiconductor chip circuitry based on attributes determined by monitoring the chip in operation.